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Preliminary 256K
X24257
400KHz 2-Wire Serial E2PROM with Block LockTM
32K x 8Bit
FEATURES * Save Critical Data with Programmable Block Lock Protection --Block Lock (first page, first 2 pages, first 4 pages, first 8 pages, 1/4, 1/2, or all of E2PROM Array) --Software Write Protection --Programmable Hardware Write Protect * In Circuit Programmable ROM Mode * 400KHz 2-Wire Serial Interface --Schmitt Trigger Input Noise Suppression --Output Slope Control for Ground Bounce Noise Elimination * Longer Battery Life With Lower Power --Active Read Current Less Than 1mA --Active Write Current Less Than 3mA --Standby Current Less Than 1A * 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power Supply Versions * 64 Byte Page Write Mode --Minimizes Total Write Time Per Word * Internally Organized 32K x 8 * Bidirectional Data Transfer Protocol * Self-Timed Write Cycle --Typical Write Cycle Time of 5ms * High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years * 8-Lead XBGA, 8-Lead SOIC, 14-Lead TSSOP FUNCTIONAL DIAGRAM
DESCRIPTION The X24257 is a CMOS Serial E2PROM, internally organized 32K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S0-S2) allow up to eight devices to share a common two wire bus. A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the device until the WEL bit in the Write Protect Register is set. The Block Lock Protection feature gives the user eight array block protect options, set by programming three bits in the Write Protect Register. The Programmable Hardware Write Protect feature allows the user to install the device with WP tied to VCC, write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are protected from being erased if WP is high.
DATA REGISTER SERIAL E2PROM DATA AND ADDRESS (SDA) SCL COMMAND DECODE AND CONTROL LOGIC BLOCK LOCK AND WRITE PROTECT CONTROL LOGIC S2 S1 S0 WP WRITE VOLTAGE CONTROL PAGE DECODE LOGIC Y DECODE LOGIC
SERIAL E2PROM ARRAY 32K x 8 WRITE PROTECT REGISTER
DEVICE SELECT LOGIC
(c)Xicor, Inc. 2000 Patents Pending 9800-5004.1 1/31/00 EP
Characteristics subject to change without notice.
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X24257
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set bits in the slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS) and they must be constant between each start and stop issued on the SDA bus. These pins have an active pull down internally and will be sensed as low if the pin is left unconnected. Write Protect (WP) WP must be constant between each start and stop issued on the SDA bus and is always active (not gated). The WP pin has an active pull down to disable the write protection when the input is left floating. The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock Protection and WPEN bits. PIN NAMES Symbol
S0, S1, S2 SDA SCL WP VSS VCC NC
Description
Device Select Inputs Serial Data Serial Clock Write Protect Ground Supply Voltage No Connect
PIN CONFIGURATION
8-Lead XBGA: Top View WP VCC SDA SCL 1 2 3 4 8 7 6 5 S1 S0 VSS S2
14 Lead TSSOP S0 S1 NC NC NC S2 VSS 1 2 3 4 5 6 7 14 13 12 X24257 11 10 9 8 VCC WP NC NC NC SCL SDA
8 Lead PDIP/SOIC S0 S1 S2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
X24257
Characteristics subject to change without notice.
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X24257
DEVICE OPERATION The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
Characteristics subject to change without notice.
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X24257
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state.
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
DEVICE ADDRESSING Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal "1010". The next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then a write operation is selected. Refer to Figure 4. After loading the Slave Address Byte from the SDA bus, the device compares the device type bits with the value "1010" and the device select bits with the status of the device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode.
On power up the internal address is undefined, so the first read or write operation must supply an address. The word address is either supplied by the master or obtained from an internal counter, depending on the operation. The master must supply the two Word Address Bytes as shown in Figure 4. The internal organization of the E2 array is 512 pages by 64 bytes per page. The page address is partially contained in the Word Address Byte 1 and partially in bits 7 through 6 of the Word Address Byte 0. The byte address is contained in bits 5 through 0 of the Word Address Byte 0. See Figure 4.
Characteristics subject to change without notice.
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X24257
Figure 4. Device Addressing
DEVICE TYPE IDENTIFIER DEVICE SELECT
1
0
1
0
S2
S1
S0
R/ W
SLAVE ADDRESS BYTE
HIGH ORDER WORD ADDRESS
*
A14 A13
A12
A11 A10
A9
A8
X24257 WORD ADDRESS BYTE 1 *This bit is 0 for access to the array and 1 for access to the Control Register
LOW ORDER WORD ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS BYTE 0
D7
D6
D5
D4
D3
D2
D1
D0
DA BYTE TA
WRITE OPERATIONS Byte Write For a write operation, the device follows "3 byte" protocol, consisting of one Slave Address Byte, one Word Address Byte 1, and the Word Address Byte 0, which gives the master access to any one of the words in the array. Upon receipt of the Word Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. The SDA pin is at high impedance. See Figure 5.
Page Write The device is capable of a 64 byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write operation after the first data word is transferred, the master can transmit up to sixty-three more words. The device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to the first byte of the current page. This means that the master can write 64 bytes to the page beginning at any byte. If the master begins writing at byte 32, and loads 64 bytes, then the first 32 bytes are written to bytes 32 through 63, and the last 16 words are written to bytes 0 through 31. Afterwards, the address counter would point to byte 32.
Characteristics subject to change without notice.
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X24257
If the master writes more than 64 bytes, then the previously loaded data is overwritten by the new data, one byte at a time. The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S T A R T WORD ADDRESS WORD ADDRESS BYTE 1 BYTE 0 0 A C K A C K A C K A C K S T O P P
SLAVE ADDRESS
DATA
S1 0 1 0
Figure 6. Page Write Sequence
(0n64) SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S T A R T SLAVE ADDRESS WORD ADDRESS WORD ADDRESS BYTE 1 BYTE 0 DATA (0) DATA (n) S T O P P A C K A C K A C K A C K A C K
S1010
0
Stop and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it's associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected.
Acknowledge Polling The maximum write cycle time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the internal write cycle, then no ACK will be returned. If the device has completed the internal write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Figure 7.
Characteristics subject to change without notice.
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X24257
Figure 7. Acknowledge Polling Sequence READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Current Address Read Internally, the device contains an address counter that maintains the address of the last word read or written incremented by one. After a read operation from the last address in the array, the counter will "roll over" to the first address in the array. After a write operation to the last address in a given page, the counter will "roll over" to the first address on the same page. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 8 for the address, acknowledge, and data transfer sequence. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
ISSUE STOP
BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING
ISSUE START
ISSUE SLAVE ADDRESS BYTE (READ OR WRITE)
ISSUE STOP
ACK RETURNED? YES
NO
HIGH VOLTAGE CYCLE COMPLETE. CONTINUE SEQUENCE?
NO
YES CONTINUE NORMAL READ OR WRITE COMMAND SEQUENCE
Figure 8. Current Address Read Sequence
SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S T A R T S T O P 1 A C K DATA P
PROCEED
SLAVE ADDRESS
S1010
Characteristics subject to change without notice.
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X24257
Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "Dummy" write operation. The master issues the start condition and the Slave Address Byte with the R/W bit low, receives an acknowledge, then issues the Word Address Byte 1, receives another acknowledge, then issues the Word Address Byte 0. After the device acknowledges receipt of the Word Address Byte 0, the master issues another start condition and the Slave Address Byte with the R/ W bit set to one. This is followed by an acknowledge and then eight bits of data from the device. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 9 for the address, acknowledge, and data transfer sequence. The device will perform a similar operation called "Set Current Address" if a stop is issued instead of the second start shown in Figure 9. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. The effect of this operation is that the new address is loaded into the address counter, but no data is output by the device. The next Current Address Read operation will read from the newly loaded address. Sequential Read Sequential reads can be initiated as either a current address read or random read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. At the end of the address space the counter "rolls over" to address 0000h and the device continues to output data for each acknowledge received. Refer to Figure 10 for the acknowledge and data transfer sequence.
Figure 9. Random Read Sequence
SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S T A R T SLAVE ADDRESS WORD ADDRESS WORD ADDRESS BYTE 1 BYTE 0 S T A R T S A C K A C K A C K SLAVE ADDRESS 1 A C K S T O P P
S1010
0
DATA
Figure 10. Sequential Read Sequence
SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE
SLAVE ADDRESS S 1 A C K
A C K
A C K
A C K
S T O P P
DATA (1)
DATA (2)
DATA (n-1)
DATA (n)
(n is any integer greater than 1)
Characteristics subject to change without notice.
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X24257
CONTROL REGISTER (CR) The Control Register is located in an area logically separated from the array and is only accessible via a byte write to the register address of FFFFH. The Control Register is physically part of the array. The Control Register can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to initiating a nonvolatile write to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. The user must issue a stop, after sending this byte to the register, to initiate the high voltage cycle that writes BP2, BP1, BP0 and WPEN to the nonvolatile bits. The part will not acknowledge any data bytes written after the first byte is entered. A stop must also be issued after a volatile register write operation to put the device into Standby. After a write to the CR, the address counter contents are undefined. The state of the Control Register can be read by performing a random read at the address of the register at any time. Only one byte is read by the register read operation. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. After the read of the CR, the address counter contents are reset to zero, but the user will be told these bits are undefined and instructed to do a random read. Table 1. Control Register 7
WPEN
6
X
5
X
4
BP1
3
BP0
2
1
0
BP2
RWEL WEL
RWEL: Register Write Enable Latch The RWEL bit must be set to "1" prior to a write to Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a "1" to the WEL bit and zeros to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeros to the other bits of the control register) or until the part powers up again. Writes to WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 2.
Table 2. Block Protect Bits BP2
0 0 0 0 1 1 1 1
BP1
0 0 1 1 0 0 1 1
BP0
0 1 0 1 0 1 0 1
Protected Addresses
None 6000h - 7FFFh (8K bytes) 4000h - 7FFFh (16K bytes) 0000h - 7FFFh (32K bytes) 0000h - 003Fh (64 bytes) 0000h - 007Fh (128 bytes) 0000h - 00FFh (256 bytes) 0000h - 01FFh (512 bytes)
Array Lock
None Upper 1/4 (Q4) Upper 1/2 (Q3, Q4) Full Array (All) First Page (P1) First 2 pgs (P2) First 4 pgs (P4) First 8 pgs (P8)
Characteristics subject to change without notice.
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X24257
Figure 11. Block Protection Configuration BP2BP0 000 001 010 011 100 101 110 111
None 1 page 2 Pages 4 Pages 8 Pages
1/2 Array
1/4 Array
Write Protect Enable Bit - WPEN - (Nonvolatile) The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the Programmable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin is HIGH and the WPEN bit is HIGH, and disabled when either the WP pin is LOW. When the chip is Hardware Write Protected, nonvolatile writes are disabled to the
Control Register, including the Block Protect bits and the WPEN bit itself, as well as to the block sections in the memory array. Only the sections of the memory array that are not block protected can be written. Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH.
Table 3. Write Protect Enable Bit and WP Pin Function WP
LOW HIGH HIGH
WPEN
X 0 1
Memory Array Not Block Protected
Writes OK Writes OK Writes OK
Memory Array Block Protected
Writes Blocked Writes Blocked Writes Blocked
Block Lock Bits
Writes OK Writes OK Writes Blocked
WPEN Bit
Writes OK Writes OK Writes Blocked
Protection
Software Software Hardware
Characteristics subject to change without notice.
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All Array
X24257
Unused Bits:
Bits 5 & 6 are unused. All writes to the Control Register must have a zero in these bit positions. The Data Byte output during a Control Register read will contain zeros in these bit locations. Writing to the Control Register Changing any of the nonvolatile bits of the control register requires the following steps: * Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). * Write a 06H to the Control Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). * Write a value to the Control Register that has all the control bits set to the desired state, with the WEL bit set to `1' and the RWEL bit set to `0'. This can be represented as n00s t01r in binary, where n is the WPEN bit and rst are the BP2-BP0 bits. (Operation preceeded by a start and ended with a stop). Since this is nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (n00s t11r) then the RWEL bit remains set and the WPEN, BP2, BP1 and BP0 bits remain unchanged. * A read operation occurring between any of the previous operations will not interrupt the register write operation. * The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits to 0 and clear the RWEL bit. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set.
Characteristics subject to change without notice.
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X24257
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias 24257.............................................-65C to +135C Storage Temperature.........................-65C to +150C Voltage on any Pin with Respect to VSS ....................................... -1V to +7V D.C. Output Current.............................................. 5mA Lead Temperature (Soldering, 10 seconds) ..................................300C RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage
X24257 X24257-2.5 X24257-1.8
Limits
4.5V to 5.5V 2.5V to 5.5V 1.8V to 3.6V
Min.
0C -40C
Max.
+70C +85C
D.C. OPERATING CHARACTERISTICS VCC equals the range indicated for each device type, unless otherwise stated.
VCC = 1.8 to 3.6V Symbol
ICC1 ICC2
VCC = 2.5 to 5.5V Min. Max.
1 3 1
VCC = 4.5 to 5.5V Min. Max.
1 3 1
Parameter
Active Supply Current (Read) Active Supply Current (Write) Standby Current AC Standby Voltage (Test) Standby Current DC Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Schmitt Trigger Input Hysteresis Fixed input level VCC related level
Min.
Max.
0.5 1.5 1
Units
mA mA mA
Test Conditions
VIL = VCC X 0.1 VIH = VCC X 0.9 fSCL = 400KHz SDA = Open VIL = VCC X 0.1 VIH = VCC X 0.9 fSCL = 400KHz SDA = Open
ISB1
(2)
VSB ISB2(2) ILI ILO VlL(3) VIH(3)
VCC- 0.1 1 10 10 -0.5 VCC x 0.7 0.2 VCC x 0.05 0.4 VCC x 0.3 VCC + 0.5
VCC- 0.2 1 10 10 -0.5 VCC x 0.7 0.2 VCC x 0.05 0.4 VCC x 0.3 VCC + 0.5
VCC- 0.3 10 10 10 -0.5 VCC x 0.7 0.2 VCC x 0.05 0.4 VCC x 0.3 VCC + 0.5
V mA mA mA V V V V V IOL = 3mA VSDA = VSCL = VSB, Others = GND or VSB VIN = GND to VCC VSDA = GND to VCC Device is in Standby(2)
VHYS
VOL
Output LOW Voltage
Characteristics subject to change without notice.
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X24257
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
CI/O(3) CIN(3)
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t WC after a stop that intiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) VIL Min. and VIH Max. are for reference only and are not tested.
Parameter Input/Output Capacitance (SDA) Input Capacitance (S0, S1, S2, SCL, WP)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10ns VCC X 0.5 Standard Output Load
EQUIVALENT A.C. LOAD CIRCUIT
5V 1.53K OUTPUT 100pF for VOL = 0.4V IOL = 3mA
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits VCC 1.8V Symbol
fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH
VCC 2.5V Min.
0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 0.9
Parameter
SCL Clock Frequency Pulse width Suppression Time at Inputs SCL LOW to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Clock LOW Period Clock HIGH Period Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time
Min.
0 n/a 0.3 4.7 4.7 4.0 4.7 4.0 250 0 4.7 300
Max.
100 n/a 3.5
Max.
400
Units
KHz ns s s s s s s ns s s ns
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Characteristics subject to change without notice.
X24257
A.C. OPERATING CHARACTERISTICS (CONTINUED) (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits VCC 1.8V Symbol
tR tF tSU:S0, S1, S2, WP tHD:S0, S1, S2, WP Cb
VCC 2.5V Min.
20+ .1Cb(3) 20+ .1Cb(3) 0.6 0
Parameter
SDA and SCL Rise Time SDA and SCL Fall Time S0, S1, S2, and WP Setup Time S0, S1, S2, and WP Hold Time Capacitive load for each bus line
Min.
Max.
1000 300
Max.
300 300
Units
ns ns ns ns
0.4 0 400
400
pF
POWER-UP TIMING(4) Symbol
tPUR tPUW
Notes: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. (5) Typical values are for TA = 25C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF.
Parameter
Power-up to Read Operation Power-up to Write Operation
Max.
1 5
Units
ms ms
Bus Timing
tF SCL tSU:STA SDA IN tAA SDA OUT t DH t BUF t HD:STA tHD:DAT t SU:DAT t SU:STO t HIGH t LOW tR
Characteristics subject to change without notice.
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X24257
S0, S1, S2, and WP Pin Timing
SCL
Clk 1 Slave Address Byte
Clk 9
SDA IN tSU: S0, S1, S2, WP S0, S1, S2, and WP tHD: S0, S1, S2, WP
Write Cycle Limits Symbol
TWC(6)
Notes: (6) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
Parameter
Write Cycle Time
Min.
--
Typ.
5
Max.
10
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24257 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Write CycleTiming
SCL
SDA
8th BIT WORD n
ACK t WC STOP CONDITION START CONDITION
Characteristics subject to change without notice.
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X24257
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120 RESISTANCE (K) 100 80 60 40 20 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF)
MIN. RESISTANCE V RMIN = CC MAX IOL MIN t RMAX = R CBUS MAX. RESISTANCE
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
Characteristics subject to change without notice.
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X24257
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice.
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X24257
PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0- 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice.
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X24257
PACKAGING INFORMATION 8-LEAD PLASTIC, 0.200" WIDE SMALL OUTLINE GULLWING PACKAGE TYP "A" (EIAJ SOIC)
0.020 (.508) 0.012 (.305)
.213 (5.41) .205 (5.21)
.330 (8.38) .300 (7.62)
PIN 1 ID
.050 (1.27) BSC
.212 (5.38) .203 (5.16)
.080 (2.03) .070 (1.78) .013 (.330) .004 (.102)
0 8
REF .010 (.254) .007 (.178)
.035 (.889) .020 (.508)
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice.
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X24257
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA Complete Part Number X24257Z-2.5 X24257ZI-2.5 X24257B-2.5 X24257BI-2.5
8-Lead XBGA: Top View .079" WP VCC SDA SCL 1 2 3 4 8 7 6 5 S1 SO VSS S2 .137" e
Top Mark XACG XACH XACG XACH
X24257: Bottom View
A1
S1
WP PIN 1
S0 C VSS
VCC
SDA
E
S2 F
SCL
D
Dwg Symbol
A A1 C D E e F
8L XBGA
Contact Factory Contact Factory Contact Factory Contact Factory Contact Factory Contact Factory Contact Factory
A
D A1 C
ALL DIMENSIONS IN M (to convert to inches, 1m = 3.94 x 10-5 inch) ALL DIMENSIONS ARE TYPICAL VALUES
Characteristics subject to change without notice.
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X24257
ORDERING INFORMATION X24257 Device X X -X V CC Range Blank = 5V 10% 2.5 = 2.5V to 5.5V 1.8 = 1.8V to 3.6V Temperature Range Blank = 0C to +70C I = -40C to +85C Package X24257 Z = 8-Lead XBGA V14 = 14-Lead TSSOP S8 = 8-Lead SOIC, 150 mil wide, JEDEC A8 = 8-Lead SOIC, 200 mil wide, EIAJ B = 8-Lead XBGA Lead TSSOP/SOIC X24257 X X V14 = 14-Lead TSSOP S8 = 8-Lead SOIC (JEDEC) A8 = 8-Lead SOIC (EIAJ) Blank = 4.5V to 5.5V, 0C to +70C I = 4.5V to 5.5V, -40C to +85C J = 2.5V to 5.5V, 0C to +70C K = 2.5V to 5.5V, -40C to +85C AG = 1.8V to 3.6V, 0C to +70C AH = 1.8V to 3.6V, -40C to +85C
PART MARK CONVENTION XBGA PACKAGE Complete Part Number Top Mark X24257Z - 2.5 X24257ZI - 2.5 X24257B - 2.5 X24257BI - 2.5 XACG XACH XACG XACH
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor andthe Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice.
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